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ISCA
2002
IEEE

An Instruction Set and Microarchitecture for Instruction Level Distributed Processing

9 years 1 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulators at the top. The instruction stream is divided into chains of dependent instructions (strands) where intra-strand dependences are passed through the accumulator. The general-purpose register file is used for communication between strands and for holding global values that have many consumers. A microarchitecture to support the proposed ISA is proposed and evaluated. The microarchitecture consists of multiple, distributed processing elements. Each PE contains an instruction issue FIFO, a local register (accumulator) and local copy of register file. The overall simplicity, hierarchical value communication, and distributed implementation will provide a very high clock speed and a relatively short pipeline while maintaining a form of superscalar out-of-order execution. Detailed timing simulations using translate...
Ho-Seop Kim, James E. Smith
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where ISCA
Authors Ho-Seop Kim, James E. Smith
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