5 search results - page 1 / 1 » Instruction buffering exploration for low energy VLIWs with ... |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
SAC
2004
ACM
13 years 10 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
IEEEPACT
2005
IEEE
13 years 10 months ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
CAMP
2005
IEEE
13 years 6 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...