5 search results - page 1 / 1 » Instruction distribution heuristics for quad-cluster, dynami... |
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
We investigate instruction distribution methods for quadcluster, dynamically-scheduled superscalar processors. We study a variety of methods with different cost, performance and c...
ICS
2001
Tsinghua U.
13 years 9 months ago
2001
Tsinghua U.
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
CF
2005
ACM
13 years 7 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
EUROPAR
2001
Springer
13 years 9 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...