29 search results - page 1 / 6 » Integrating BIST Techniques for On-Line SoC Testing |
IOLTS
2005
IEEE
13 years 10 months ago
2005
IEEE
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
DSN
2005
IEEE
13 years 10 months ago
2005
IEEE
1 In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems’ depe...