5 search results - page 1 / 1 » Integrating buffer planning with floorplanning for simultane... |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
ICCAD
2002
IEEE
13 years 9 months ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
WSC
1998
13 years 6 months ago
1998
Selecting an optimum maintenance policy independent of other parameters of the production system does not always yield the overall optimum operating conditions. For instance, high...