17 search results - page 4 / 4 » Integration of Clock Skew and Register Delays into a Retimin... |
ISPD
2003
ACM
13 years 11 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...