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ISQED
2007
IEEE
114views Hardware» more  ISQED 2007»
13 years 11 months ago
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure
Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncoveri...
Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Ch...
ATS
2000
IEEE
145views Hardware» more  ATS 2000»
13 years 9 months ago
Compaction-based test generation using state and fault information
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwa...
ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
14 years 1 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
ICCAD
2002
IEEE
143views Hardware» more  ICCAD 2002»
14 years 1 months ago
A Markov chain sequence generator for power macromodeling
In macromodeling-based power estimation, circuit macromodels are created from simulations of synthetic input vector sequences. Fast generation of these sequences with all possible...
Xun Liu, Marios C. Papaefthymiou
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 2 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang