42 search results - page 1 / 9 » Interconnect Delay Estimation Models for Synthesis and Desig... |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...