Sciweavers

154 search results - page 31 / 31
» Interconnect Optimization Strategies for High-Performance VL...
Sort
View
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 8 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ICS
2009
Tsinghua U.
13 years 11 months ago
/scratch as a cache: rethinking HPC center scratch storage
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
Henry M. Monti, Ali Raza Butt, Sudharshan S. Vazhk...
ANCS
2007
ACM
13 years 8 months ago
Towards high-performance flow-level packet processing on multi-core network processors
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
Yaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu...
TASE
2008
IEEE
13 years 4 months ago
Steady-State Throughput and Scheduling Analysis of Multicluster Tools: A Decomposition Approach
Abstract--Cluster tools are widely used as semiconductor manufacturing equipment. While throughput analysis and scheduling of single-cluster tools have been well-studied, research ...
Jingang Yi, Shengwei Ding, Dezhen Song, Mike Tao Z...