44 search results - page 3 / 9 » Interconnect design considerations for large NUCA caches |
MICRO
2009
IEEE
14 years 12 days ago
2009
IEEE
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
ICDCS
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper introduces volume leases as a mechanism for providing cache consistency for large-scale, geographically distributed networks. Volume leases are a variation of leases, w...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
ISPD
1997
ACM
13 years 10 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...