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MICRO
2009
IEEE

Variation-tolerant non-uniform 3D cache management in die stacked multicore processor

8 years 11 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation of 3D stacking technology, DRAMs become a favorable choice for stacking on top of a multicore processor as a last level cache for large capacity, high bandwidth, and low power. Hence, variations in bank speed creates a unique problem of non-uniform cache accesses in 3D space. In this paper, we investigate cache management techniques for tolerating process variation in a 3D DRAM stacked onto a multicore processor. We modeled the process variation in a 4-layer DRAM memory to characterize the latency variations among different banks. As a result, the notion of fast and slow banks from th...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
Added 24 May 2010
Updated 24 May 2010
Type Conference
Year 2009
Where MICRO
Authors Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
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