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» Interconnect design for deep submicron ICs
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TCAD
2002
99views more  TCAD 2002»
13 years 5 months ago
Analysis of on-chip inductance effects for distributed RLC interconnects
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
Kaustav Banerjee, Amit Mehrotra
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
13 years 9 months ago
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L....
DAC
1998
ACM
13 years 9 months ago
Global Routing with Crosstalk Constraints
—Due to the scaling down of device geometry and increasing of frequency in deep submicron designs, crosstalk between interconnection wires has become an important issue in very l...
Hai Zhou, D. F. Wong
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
13 years 11 months ago
Wire-driven microarchitectural design space exploration
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...
Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram,...
DAC
1996
ACM
13 years 9 months ago
VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems
This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...
Bernhard Wunder, Gunther Lehmann, Klaus D. Mü...