34 search results - page 6 / 7 » Interconnect power and delay optimization by dynamic program... |
EAAI
2006
13 years 5 months ago
2006
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
FPL
2001
Springer
13 years 10 months ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
ICCD
2008
IEEE
14 years 2 months ago
2008
IEEE
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
ASPDAC
2009
ACM
13 years 12 months ago
2009
ACM
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...