57 search results - page 2 / 12 » Interconnect-power dissipation in a microprocessor |
EUROMICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Two years ago [3] we began to study a R.I.S.C. approachfor smart card microprocessors. We reconsider this research to answer the question of the new technology of smart cards: the...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
MICRO
2000
IEEE
13 years 4 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
ERSA
2009
13 years 2 months ago
2009
Abstract-- The paper presents the implementation of nonlinear least-squares regression in a Field Programmable Gate Array (FPGA) device. The implemented algorithm is very performan...
ISQED
2011
IEEE
12 years 8 months ago
2011
IEEE
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors...