60 search results - page 1 / 12 » Interface Design for Rationally Clocked GALS Systems |
ASYNC
2006
IEEE
13 years 11 months ago
2006
IEEE
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
ASYNC
2002
IEEE
13 years 10 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...