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ISLPED
2005
ACM

System level power and performance modeling of GALS point-to-point communication interfaces

9 years 2 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising technique in the system on a chip (SoC) era. In the context of today’s increasingly complex SoCs, there is a need for design methodologies that start r levels of abstraction. Much of the previous work has been devoted to design of asynchronous communication schemes such as mixed clock FIFOs and pausible clocks for globally asynchrocally synchronous systems, but at low levels of abstraction, such as circuit level. To enable early design evaluation of such schemes, this paper proposes to use a SystemC-based modeling methodology for the asynchronous communication among various locally synchronous islands. The modeling framework encompasses various levels of abstraction and enables system-level validation of circuit or RT level hardware descriptions, as well as their impact on high-level design decisions. Categ...
Koushik Niyogi, Diana Marculescu
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ISLPED
Authors Koushik Niyogi, Diana Marculescu
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