Sciweavers

44 search results - page 2 / 9
» Intrabody Buses for Data and Power
Sort
View
ICCAD
2006
IEEE
102views Hardware» more  ICCAD 2006»
14 years 2 months ago
Optimal memoryless encoding for low power off-chip data buses
Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Li...
DSD
2003
IEEE
84views Hardware» more  DSD 2003»
13 years 10 months ago
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, ...
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
13 years 9 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...
APCCAS
2006
IEEE
304views Hardware» more  APCCAS 2006»
13 years 11 months ago
Low-Power Bus Transform Coding for Multilevel Signals
Abstract— In this paper, we propose a novel extension of BusInvert coding to handle 4-level pulse amplitude modulated (PAM-4) signals. A generalized mathematical model for energy...
Fakhrul Zaman Rokhani, Gerald E. Sobelman
HIPC
2003
Springer
13 years 10 months ago
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses
Power consumption becomes an important issue for modern processors. The off-chip buses consume considerable amount of total power [9,7]. One effective way to reduce power is to red...
Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, B...