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» Introspective 3D chips
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ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
13 years 11 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
TCAD
2002
123views more  TCAD 2002»
13 years 5 months ago
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
Abstract--Recent study shows that the nonuniform thermal distribution not only has an impact on the substrate but also interconnects. Hence, three
Ting-Yuan Wang, Charlie Chung-Ping Chen
ASPDAC
2009
ACM
153views Hardware» more  ASPDAC 2009»
13 years 3 months ago
A 3D prototyping chip based on a wafer-level stacking technology
We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stac...
Nobuaki Miyakawa
ICCAD
2008
IEEE
161views Hardware» more  ICCAD 2008»
14 years 2 months ago
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu ...