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    ISCA
    2009
    IEEE
    123views Hardware» more  ISCA 2009»
    InvisiFence: performance-transparent memory ordering in conventional multiprocessors
    13 years 11 months ago
    InvisiFence: performance-transparent memory ordering in conventional multiprocessors
    Download  www.cis.upenn.edu
    Colin Blundell, Milo M. K. Martin, Thomas F. Wenis...
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    CAL
    2010
    145views Software Engineering» more  CAL 2010»
    SMT-Directory: Efficient Load-Load Ordering for SMT
    13 years 1 months ago
    SMT-Directory: Efficient Load-Load Ordering for SMT
    Download  www.cis.upenn.edu
    Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
    A. Hilton, A. Roth
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    ISCA
    2007
    IEEE
    145views Hardware» more  ISCA 2007»
    Mechanisms for store-wait-free multiprocessors
    13 years 11 months ago
    Mechanisms for store-wait-free multiprocessors
    Download  www.eecg.toronto.edu
    Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
    Thomas F. Wenisch, Anastassia Ailamaki, Babak Fals...
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    CF
    2009
    ACM
    138views Applied Computing» more  CF 2009»
    A light-weight fairness mechanism for chip multiprocessor memory systems
    13 years 11 months ago
    A light-weight fairness mechanism for chip multiprocessor memory systems
    Download  www.idi.ntnu.no
    Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
    Magnus Jahre, Lasse Natvig
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