48 search results - page 2 / 10 » Issues and Support for Dynamic Register Allocation |
EUROMICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
HPCA
1996
IEEE
13 years 9 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
HPCA
2012
IEEE
12 years 1 months ago
2012
IEEE
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
ASAP
2004
IEEE
13 years 9 months ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...