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» LLVA: A Low-level Virtual Instruction Set Architecture
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IEEEHPCS
2010
13 years 3 months ago
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms a...
Shivani Raghav, Martino Ruggiero, David Atienza, C...
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
13 years 9 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 7 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
CASES
2007
ACM
13 years 9 months ago
A fast and generic hybrid simulation approach using C virtual machine
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to i...
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Asch...
WSC
1997
13 years 6 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson