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VTS
2002
IEEE
120views Hardware» more  VTS 2002»
13 years 10 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
VTS
2008
IEEE
119views Hardware» more  VTS 2008»
13 years 11 months ago
Error Sequence Analysis
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
Jaekwang Lee, Intaik Park, Edward J. McCluskey