3 search results - page 1 / 1 » Large multipliers with fewer DSP blocks |
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
TIP
1998
13 years 5 months ago
1998
Abstract—In this paper, we propose an optimal quadtree (QT)based motion estimator for video compression. It is optimal in the sense that for a given bit budget for encoding the d...