248 search results - page 49 / 50 » Layered Switching for Networks on Chip |
SAMOS
2004
Springer
13 years 10 months ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
CF
2006
ACM
13 years 9 months ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
INFOCOM
2009
IEEE
14 years 17 hour ago
2009
IEEE
—Enterprise networks are increasingly adopting Layer 3 Multiprotocol Label Switching (MPLS) Virtual Private Network (VPN) technology to connect geographically disparate locations...
INFOCOM
2003
IEEE
13 years 10 months ago
2003
IEEE
— Multiprotocol Label Switching or MPLS technology is being increasingly deployed by several of the largest Internet service providers to solve problems such as traffic engineer...