4 search results - page 1 / 1 » Layout Optimization Using Arbitrarily High Degree Posynomial... |
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
JGAA
2007
13 years 4 months ago
2007
The cluster structure of many real-world graphs is of great interest, as the clusters may correspond e.g. to communities in social networks or to cohesive modules in software syst...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
ICCAD
2006
IEEE
13 years 11 months ago
2006
IEEE
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...