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» Layout aware design of mesh based NoC architectures
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IESS
2007
Springer
165views Hardware» more  IESS 2007»
13 years 11 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
13 years 2 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan
DAC
2006
ACM
13 years 10 months ago
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...
Ming Li, Qing-An Zeng, Wen-Ben Jone
DAC
2004
ACM
13 years 10 months ago
Fast and accurate parasitic capacitance models for layout-aware
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanch...
MOBIHOC
2005
ACM
14 years 4 months ago
Interference-aware topology control and QoS routing in multi-channel wireless mesh networks
The throughput of wireless networks can be significantly improved by multi-channel communications compared with single-channel communications since the use of multiple channels ca...
Jian Tang, Guoliang Xue, Weiyi Zhang