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ASPLOS
1991
ACM
13 years 8 months ago
LimitLESS Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
David Chaiken, John Kubiatowicz, Anant Agarwal
IPPS
1999
IEEE
13 years 9 months ago
Segment Directory Enhancing the Limited Directory Cache Coherence Schemes
We present a new arrangement of directory bits called the segment directory to improve directory storage efficiency: a segment directory can point to several sharing processors wi...
Jong Hyuk Choi, Kyu Ho Park
ICPP
1990
IEEE
13 years 9 months ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry
MICRO
2010
IEEE
99views Hardware» more  MICRO 2010»
13 years 2 months ago
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also called chunks) can boost the programmability and performance of shared-memory mult...
Xuehai Qian, Wonsun Ahn, Josep Torrellas
MICRO
2010
IEEE
159views Hardware» more  MICRO 2010»
13 years 2 months ago
Fractal Coherence: Scalably Verifiable Cache Coherence
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, t...
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin