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DCG
2011
12 years 12 months ago
Lines Pinning Lines
Boris Aronov, Otfried Cheong, Xavier Goaoc, Gü...
ISCAS
2005
IEEE
135views Hardware» more  ISCAS 2005»
13 years 10 months ago
Dual use of power lines for data communications in a system-on-chip environment
—We propose to use power pins to simultaneously carry data signals while delivering its power. A direct superposition of a data signal on a power pin would fail due to an inheren...
Woo Cheol Chung, Dong Sam Ha, Hyung-Jin Lee
ASPDAC
1999
ACM
137views Hardware» more  ASPDAC 1999»
13 years 9 months ago
A Performance-Driven I/O Pin Routing Algorithm
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arun...
IPPS
2006
IEEE
13 years 11 months ago
Performance evaluation of wormhole routed network processor-memory interconnects
Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processormemory environments, to ...
Taskin Koçak, Jacob Engel
ISCAS
2007
IEEE
136views Hardware» more  ISCAS 2007»
13 years 11 months ago
Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters
—A novel feed-forward pulse width modulation (FF-PWM) technique is proposed for improving line regulation of buck or boost (BOB) converters. In order to provide a regulated suppl...
Huan-Jen Yang, Ke-Horng Chen, Yung-Pin Lee