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» Liveness and Boundedness of Synchronous Data Flow Graphs
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ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 8 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
ICCAD
2000
IEEE
149views Hardware» more  ICCAD 2000»
13 years 9 months ago
Dynamic Response Time Optimization for SDF Graphs
Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods ...
Dirk Ziegenbein, Jan Uerpmann, Ralph Ernst
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
13 years 9 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
ACMMSP
2006
ACM
226views Hardware» more  ACMMSP 2006»
13 years 9 months ago
Smarter garbage collection with simplifiers
We introduce a method for providing lightweight daemons, called simplifiers, that attach themselves to program data. If a data item has a simplifier, the simplifier may be run aut...
Melissa E. O'Neill, F. Warren Burton
CIKM
2008
Springer
13 years 7 months ago
An extended cooperative transaction model for xml
In many application areas, for example in design or media production processes, several authors have to work cooperatively on the same project. Thereby, a frequently used data for...
Francis Gropengießer, Kai-Uwe Sattler