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» Location cache: a low-power L2 cache system
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ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
13 years 10 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
13 years 9 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
HIPEAC
2009
Springer
13 years 8 months ago
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
IPPS
2006
IEEE
13 years 10 months ago
Enhancing L2 organization for CMPs with a center cell
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-chip transistors. At the same time, the location of data on the chip can play a c...
Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemi...
HPCA
2005
IEEE
14 years 5 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...