22 search results - page 2 / 5 » LogTM-SE: Decoupling Hardware Transactional Memory from Cach... |
PLDI
2009
ACM
13 years 11 months ago
2009
ACM
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
IESS
2009
Springer
13 years 2 months ago
2009
Springer
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
PARCO
2003
13 years 6 months ago
2003
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...