233 search results - page 1 / 47 » Logic design for low-voltage low-power CMOS circuits |
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
IWSOC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Abstract--A novel input and output biasing circuit to extend the input common mode (CM) voltage range and the output swing to rail-to-rail in a low voltage op-amp in standard CMOS ...
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...