Sciweavers

20 search results - page 1 / 4
» Logical Verification of the NVAX CPU Chip Design
Sort
View
ICCD
1992
IEEE
83views Hardware» more  ICCD 1992»
13 years 8 months ago
Logical Verification of the NVAX CPU Chip Design
ct Digital's NVAX high-performance microprocessor has a complex logical design. A rigorous simulation-based verification effort was undertaken to ensure that there were no log...
Walker Anderson
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 9 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
FMCAD
2007
Springer
13 years 11 months ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
FMCAD
2006
Springer
13 years 8 months ago
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include init...
Tilman Glökler, Jason Baumgartner, Devi Shanm...
DAC
2001
ACM
14 years 5 months ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...