116 search results - page 2 / 24 » Logical effort based technology mapping |
DAC
1998
ACM
14 years 6 months ago
1998
ACM
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
TCAD
2008
13 years 5 months ago
2008
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
GLVLSI
2007
IEEE
14 years 4 days ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...