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» Loop Striping: Maximize Parallelism for Nested Loops
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IPPS
1998
IEEE
13 years 10 months ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 9 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
COMAD
2008
13 years 7 months ago
Exploiting Asynchronous IO using the Asynchronous Iterator Model
Asynchronous IO (AIO) allows a process to continue to do other work while an IO operation initiated earlier completes. AIO allows a large number of random IO operations to be issu...
Suresh Iyengar, S. Sudarshan, Santosh Kumar 0002, ...
CC
2006
Springer
124views System Software» more  CC 2006»
13 years 9 months ago
Polyhedral Code Generation in the Real World
The polyhedral model is known to be a powerful framework to reason about high level loop transformations. Recent developments in optimizing compilers broke some generally accepted ...
Nicolas Vasilache, Cédric Bastoul, Albert C...
ASPLOS
2008
ACM
13 years 7 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August