Sciweavers

4 search results - page 1 / 1
» Loop unrolling and shifting for reconfigurable architectures
Sort
View
FPL
2008
Springer
109views Hardware» more  FPL 2008»
13 years 6 months ago
Loop unrolling and shifting for reconfigurable architectures
Loops are an important source of optimization. In this paper, we propose an extension to our work on loop unrolling and loop shifting for reconfigurable architectures. By applying...
Ozana Silvia Dragomir, Todor Stefanov, Koen Bertel...
ARC
2008
Springer
112views Hardware» more  ARC 2008»
13 years 7 months ago
Optimal Unroll Factor for Reconfigurable Architectures
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...
Ozana Silvia Dragomir, Elena Moscu Panainte, Koen ...
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
13 years 8 months ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
13 years 9 months ago
Matching and searching analysis for parallel hardware implementation on FPGAs
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
Pablo Moisset, Pedro C. Diniz, Joonseok Park