6 search results - page 1 / 2 » Low power BIST design by hypergraph partitioning: methodolog... |
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
DFT
2005
IEEE
13 years 7 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The new standard DRM for digital radio broadcast in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently desi...