173 search results - page 3 / 35 » Low power and low voltage CMOS digital circuit techniques |
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
This paper discusses a number of circuit techniques which address the DC and AC distortion performance of a low power current steering Digital-to-Analog Converter design. The desi...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
ISLPED
2009
ACM
13 years 10 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...