67 search results - page 12 / 14 » Low power architecture for high speed packet classification |
ISCA
2008
IEEE
14 years 15 hour ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
CF
2006
ACM
13 years 11 months ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...
VLSID
2007
IEEE
14 years 6 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
SECON
2010
IEEE
13 years 3 months ago
2010
IEEE
We introduce iPoint, a passive device that can interact and deliver information to virtually any mobile phone equipped with a WiFi network interface and a camera. The iPoint does n...
WICON
2008
13 years 7 months ago
2008
In a tree-based ZigBee network, ZigBee routers (ZRs) must schedule their beacon transmission times to avoid beacon collisions. The beacon schedule determines packet delivery laten...