67 search results - page 2 / 14 » Low power architecture for high speed packet classification |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
GLOBECOM
2009
IEEE
13 years 8 months ago
2009
IEEE
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
IPPS
2008
IEEE
13 years 11 months ago
2008
IEEE
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
ANCS
2009
ACM
13 years 2 months ago
2009
ACM
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...