67 search results - page 4 / 14 » Low power architecture for high speed packet classification |
DAC
1999
ACM
13 years 9 months ago
1999
ACM
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
DAC
1998
ACM
14 years 6 months ago
1998
ACM
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is ...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
A novel low power ripple-precharge Ternary CAM (RPTCAM) architecture is proposed for applicationsin longest prefix matching tasks. The main motivation behind this research is to ...