67 search results - page 5 / 14 » Low power architecture for high speed packet classification |
ICMCS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper proposes a practical content-dependent lowpower DCT design with tolerable quality drop. Lowpower issue has become more and more important, especially for portable devic...
ISVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
Many network security applications require large virus signature sets to be maintained, retrieved, and compared against the network streams. Software applications frequently fail ...
HPCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
AHS
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
ICC
2008
IEEE
14 years 7 days ago
2008
IEEE
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...