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VLSISP
2008
147views more  VLSISP 2008»
13 years 3 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
ISQED
2002
IEEE
168views Hardware» more  ISQED 2002»
13 years 10 months ago
ALBORZ: Address Level Bus Power Optimization
In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the l...
Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
ICASSP
2011
IEEE
12 years 9 months ago
Data-path and memory error compensation technique for low power JPEG implementation
This paper presents a novel technique to mitigate effects of datapath and memory errors in JPEG implementations. These errors are mainly caused by voltage scaling and process vari...
Yunus Emre, Chaitali Chakrabarti
TVLSI
2002
102views more  TVLSI 2002»
13 years 4 months ago
Power-optimal encoding for a DRAM address bus
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
Wei-Chung Cheng, Massoud Pedram
CASES
2003
ACM
13 years 10 months ago
Power efficient encoding techniques for off-chip data buses
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...