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» Low-latency scheduling in large switches
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RTAS
2008
IEEE
13 years 11 months ago
A Switch Design for Real-Time Industrial Networks
The convergence of computers and the physical world is the theme for next generation networking research. This trend calls for real-time network infrastructure, which requires a h...
Qixin Wang, Sathish Gopalakrishnan, Xue Liu, Lui S...
RTAS
2006
IEEE
13 years 11 months ago
Switch Scheduling and Network Design for Real-Time Systems
The rapid need for high bandwidth and low latency communication in distributed real-time systems is driving system architects towards high-speed switches developed for high volume...
Sathish Gopalakrishnan, Marco Caccamo, Lui Sha
ASPLOS
1992
ACM
13 years 9 months ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
GLOBECOM
2007
IEEE
13 years 11 months ago
OBIG: the Architecture of an Output Buffered Switch with Input Groups for Large Switches
—Large, fast switches require novel approaches to architecture and scheduling. In this paper, we propose the Output Buffered Switch with Input Groups (OBIG). We present simulatio...
Wladek Olesinski, Hans Eberle, Nils Gura
ICC
2008
IEEE
126views Communications» more  ICC 2008»
13 years 11 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...