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» Low-latency scheduling in large switches
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ICC
2007
IEEE
14 years 9 days ago
Power Managed Packet Switching
— High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos
DFT
2008
IEEE
151views VLSI» more  DFT 2008»
13 years 7 months ago
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris...
ONDM
2000
13 years 7 months ago
Distributed Router Architecture for Packet-Routed Optical Networks
: A new proposal for an optical packet-routed network based on a distributed router architecture in a WDM network is described. Buffering, scheduling and wavelength assignment func...
Michael Düser, Eugene Kozlovski, Robert I. Ki...
GLOBECOM
2009
IEEE
14 years 22 days ago
Crosstalk-Preventing Scheduling in AWG-Based Cell Switches
—AWG-based optical switching fabrics are affected by coherent crosstalk, that can significantly impair system operation when the same wavelength is used simultaneously on severa...
Andrea Bianco, David Hay, Fabio Neri
INFOCOM
2003
IEEE
13 years 11 months ago
Local Scheduling Policies in Networks of Packet Switches with Input Queues
— A significant research effort has been devoted in recent years to the design of simple and efficient scheduling policies for Input Queued (IQ) and Combined Input Output Queue...
Marco Ajmone Marsan, Paolo Giaccone, Emilio Leonar...