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ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
13 years 11 months ago
Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
Sherif A. Tawfik, Volkan Kursun
DAC
1999
ACM
13 years 9 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
DAC
1997
ACM
13 years 9 months ago
Tools and Methodologies for Low Power Design
-- Designing for low power has become increasingly important in a wide variety of applications, including wireless telephony, mobile computing, high performance computing, and high...
Jerry Frenkil
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 9 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad