2 search results - page 1 / 1 » Low-power process-variation tolerant arithmetic units using ... |
ISLPED
2007
ACM
13 years 7 months ago
2007
ACM
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...