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ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 3 months ago
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Abstract--As a replacement for the fast-fading GloballySynchronous model, we have defined a flexible design style called GRLS, for Globally-Ratiochronous, Locally-Synchronous, whic...
Jean-Michel Chabloz, Ahmed Hemani
VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
14 years 6 months ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards
CL
2010
Springer
13 years 5 months ago
SystemJ: A GALS language for system level design
In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally...
Avinash Malik, Zoran Salcic, Partha S. Roop, Alain...
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
13 years 9 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
13 years 9 months ago
Mixed-clock issue queue design for energy aware, high-performance cores
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
Venkata Syam P. Rapaka, Emil Talpes, Diana Marcule...