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    TVLSI
    2010
    149views Artificial Intelligence» more  TVLSI 2010»
    A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
    12 years 11 months ago
    A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
    Download  cadal.cse.nsysu.edu.tw
    Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...
    Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
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    ESTIMEDIA
    2006
    Springer
    127views Multimedia» more  ESTIMEDIA 2006»
    Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
    13 years 8 months ago
    Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
    Download  ihome.ust.hk
    Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm ...
    Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 6 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    VLSID
    2002
    IEEE
    128views VLSI» more  VLSID 2002»
    System-Level Point-to-Point Communication Synthesis using Floorplanning Information
    14 years 5 months ago
    System-Level Point-to-Point Communication Synthesis using Floorplanning Information
    Download  www.gigascale.org
    : In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...
    Jingcao Hu, Yangdong Deng, Radu Marculescu
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    ICCAD
    2004
    IEEE
    96views Hardware» more  ICCAD 2004»
    M-trie: an efficient approach to on-chip logic minimization
    14 years 1 months ago
    M-trie: an efficient approach to on-chip logic minimization
    Download  research.cs.tamu.edu
    Seraj Ahmad, Rabi N. Mahapatra
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