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» MAPS: multi-algorithm parallel circuit simulation
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ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
14 years 2 months ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
TCAD
2002
146views more  TCAD 2002»
13 years 5 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
TVLSI
2002
130views more  TVLSI 2002»
13 years 5 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
GECCO
2007
Springer
169views Optimization» more  GECCO 2007»
13 years 11 months ago
An evolutionary platform for developing next-generation electronic circuits
In this paper, a new method for evolving simple electronic circuits is discussed, with the aim of improving the reliability and performance of basic circuit blocks. Next-generatio...
James A. Hilder, Andy M. Tyrrell
HICSS
1996
IEEE
102views Biometrics» more  HICSS 1996»
13 years 9 months ago
Evaluation of Parallel Logic Simulation Using DVSIM
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
Gerd Meister